Design of Image Recognition Accelerator Based on FPGA

Fengjuan Miao, Yiming Wang, Bairui Tao

Abstract


Based on the application of convolutional neural network (CNN) in the field of image recognition and the characteristics of a large number of computing requirements, this paper designs an accelerator based on SDSoC (Software-defined on-chip programmable system). The key parameters of the CNN training structure file and the selection of the appropriate excitation function ReLU (Rectifiedlinearunit) for training the convolutional neural network on the virtual machine are mainly modified. Finally, a CNN hardware accelerator with shorter image recognition time and high precision is realized. The experimental results show that compared with the traditional CPU, the recognition accuracy is increased to about 78%, and the recognition time is shortened from 10 seconds to the millisecond of the general CPU.

Keywords


Image Recognition; Accelerator; Excitation Function; Accuracy; Network Structure


DOI
10.12783/dtcse/iciti2018/29175

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